Maxime Pelcat

Dr. Maxime Pelcat is an Associate Professor at INSA Rennes. He holds a research appointment at IETR in Rennes, the 6164 CNRS research unit. Maxime Pelcat obtained his Habilitation (HDR) in hardware architecture for signal processing from Université Clermont Auvergne in 2017, and his Ph.D. in signal processing from INSA Rennes in 2010 in collaboration with Texas Instruments. Previously, after one year in the Audio and Multimedia department at Fraunhofer Institute IIS in Erlangen, Germany, he worked as a contractor at France Telecom Research and Development until 2006. He is an author of more than 80 peer reviewed publications in the domains of models of computation, models of architecture, systems efficiency, system design productivity, multimedia and telecommunication processing, programming of parallel embedded systems and hardware security. Maxime Pelcat has been a member of technical programs of SAMOS-IC, PDP, MEMOCODE, EDERC, ICDSC, GlobalSIP, ReCoSoC and SiPS. He is an associate editor of the Springer Journal of Signal Processing Systems. He has been program chair of SAMOS-IC 2019 and is general chair of the 2020 GDR SOC2 colloquium and SiPS 2022 conference. He has participated to 1 H2020 ICT, 1 H2020 ITN, 1 NSF, 1 FUI, and 2 ANR projects. Maxime Pelcat has been an elected member of CNRS national committee CoNRS, Section 07 "Information Science" from 2018 to 2021. He is an author of the book "Physical Layer Multi-Core Prototyping" Springer, 2012.

https://mpelcat.org