Courriel : maria [dot] mendez [at] univ-nantes [dot] fr
Téléphone : +33 (0)2 40 68 30 21
Numéro de bureau : Polytech Nantes - C110ireste
* Publications in 2023
- "You Only Get One-Shot: Eavesdropping Input Images to Neural Network by Spying SoC-FPGA Internal Buses", M. Myat Thu, M. Méndez Real, M.Pelcat, P. Besnier, in ARES, 2023.
- "Securing a RISC-V architecture: A dynamic approach", S. Pillement, M. Méndez Real, et al., in DATE, 2023.
- "Bus Electrocardiogram: Vulnerability of SoC-FPGA Internal AXI Buses to Electromagnetic Side-Channel Analysis", M. Myat Thu, M.Méndez Real, M. Pelcat, P. Besnier, in EMC Europe, 2023.
* PC member of TCHES'23, TCHES'24
Originally from Mexico, Maria Méndez Real spent one year in the United States and lives in France since 2009.
Since September 2018, Maria Méndez Real is Associate Professor (Maitre de Conférences) at Polytech Université de Nantes, France. Since 2014 she has been working in Hardware Security. Her reasearch activity is within IETR (Institut d’Electronique et des Technologies du numéRique, UMR CNRS 6164) lab. Her research interests are on side-channel attacks, fault and remote attacks, embedded systems, multi and many-core systems and protoyping tools.
From 2017 to 2018 she was an Assistant Professor (ATER) at Polytech Université de Nantes.
In 2015 she was invited researcher at the Ruhr-University of Bochum (RUB), Germany. She worked on virtual prototyping tools for evaluating multi core architectures security.
In 2017, she received her PhD, european label, in Electronic Engineering - Hardware Security from UBS (Université de Bretagne-Sud), within Lab-STICC UMR 6285 lab in France. Her PhD work was on the frame of the French ANR TSUNAMY project (2013-2017) and deal with secure-enable mechanisms for the physical isolation of sensitive applications on many-core architectures.
Before that, she received her master (Dipl.-Ing.) in Electrical and Computer from UBS in 2014.
She is author and co-author in international journals, conferences and workshops (TECS, TC, DATE, JSA, FPL, SAMOS, VLSI, etc). She is PC member and reviwer of several international journals and conferences (JCEN, DATE, NEWCAS, FPT, TCAD, LASCAS, MCSoC, ICCS, etc).
She is PC member of TCHES 2023.
She actively participates on national project evaluation (ANR projects, PEC, regional, etc) and jurys for recrutement of Associate Professors and PhD following and defense jurys.
- Juliette Pottier (2022-2025), Cache memory protection through obfuscation
- May Myat Thu (2021-2024), Study of Side-Channel Vulnerabilities in Deep Learning FPGA Implementations of Computer Vision
- Safouane Noubir (2018-2021), Investigation of Security Vulnerabilities of Energy Management on Multi-Core Architectures
Research Projects and Fundings
- VAVIECA: Side-Channel Attacks vulnerabilities on FPGA Deep Neural Networks implementions (scientific leader)
Funding: DGA through PEC (Pôle d'Excellence Cyber) (140KE)
- SecV: Processor obfuscation through dynamical instruction decoding
Funding: ANR PRC (736KE)
- SecureIoT (laureate, scientific leader)
Funding: RFI WISE Attractivité (135KE)
- SEROIF: SEcursation des Réseaux d’Objets interconnectés et de l’information pour l’Industrie du Futur (participant)
Funding: RFI WISE International, mobility (9KE)
- TRUST: Towards Reconfigurable and Secured Industrial IoT (participant)
Funding: RFI WISE, mobility (10KE)
- NOPE: Normally-Off Computing (participant)
Funding: Cominlabs, Exploratory action
- Exploration of security and reliability compatibility (scientific leader)
Funding: PEPS IETR (3,6KE)
- TSUNAMY: Hardware and software managemenT of data SecUrity iN A ManY core platform (PhD, participant)
Funding: ANR PRC (573KE)
- Referent for cyber security activities of IETR lab, ligérien perimeter (since 2019)
- Co-referent of Transversal Axis CYbersecurité Matérielle (CYM) of IETR lab (since 2021)
- Referent of IETR lab and INSIS institute, member of the CNRS Cybersecurity Miroir research group (since 2021)
- Referent for EEA club (since 2018)