Embedded system architecture
In this track of research, the team is interested in the optimized use of dynamically reconfigurable and massively parallelized hardware architectures representing a strong trend in embedded systems of today and tomorrow. This type of architecture requires the development of specific CAD models and tools at the heart of the team's research activities.
For instance, an important area of study is that of the design of fault tolerant circuits which require the search for suitable hardware architectures and the development of intelligent configuration tools, for the detection and location of faults in particular.
Management of embedded architectures
In this area, the activities focus more on the effective management and design methods of the reconfigurable architectures described above. Here we point to the optimization of the dynamic component responsible for the reconfiguration of the platform. The objective of the work is to describe the architectures in a formal way, and to propose a suite of generic tools allowing the compilation of applications for this architecture.
The team is particularly interested in the development of complete design flows and efficient operating methods for this type of architecture. One of the major problems is then to deploy the targeted applications on the architecture by optimizing both performance but also consumption and reliability.
The evolution of architectures towards multi-processor systems sharing shared resources (memory, bus, etc.) requires the implementation of validation processes early in the design flow, as well as monitoring methods making it possible to observe the execution of the system and to check its operational safety, for example. Often based on simulation approaches, these classic approaches do not take into account runtime variability due to shared elements and do not scale up given the number of components in modern systems. In this topic, the team is thus interested in the study of innovative and generic approaches to allow the performance evaluation of future multi-processor systems.
The work carried out takes into account in particular the problem of operating systems in real time, and the development of joint hardware / software processing mechanisms for operational safety in particular.